GPR-CPU (16-bit GPR CPU Emulator)
A fully functional, educational 16-bit RISC-style CPU emulator in C++ with 8 general-purpose registers, 64KB memory, and an explicit Fetch–Decode–Execute (FDE) cycle.
C++EmulatorRISC
What It Does
This project is a functional 16-bit RISC CPU emulator designed to simulate the fetch-decode-execute cycle of a custom Load/Store architecture. It mirrors the behavior of hardware by managing state across a dedicated register file, a 64KB memory space, and a synchronous bus system.
⚙️ Core Architecture
The emulator implements a streamlined RISC (Reduced Instruction Set Computer) design, featuring:
- Register File: Eight 16-bit General Purpose Registers ($R_0$ through $R_7$) and a dedicated Program Counter (PC).
- Status Flags: A hardware-level FLAGS register that tracks arithmetic state: Zero (Z), Carry (C), and Negative (N).
- Memory Model: A linear 64KB address space, word-addressed (16-bit) for efficient data handling.
📜 Instruction Pipeline
The CPU processes instructions via a fixed-length 16-bit encoding scheme, ensuring predictable decoding logic:
- Opcode: High 4 bits define the operation (supporting up to 16 unique instructions).
- Operand Mapping: Dedicated bit-fields for Destination ($R_d$) and Source ($R_s$) registers.
- Immediate Support: Supports 6-bit immediate values for operations like MOVI (Move Immediate).